1. Field of Invention
Various embodiments of the present disclosure relate to substrates used in the fabrication of semiconductor packages and, also to substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same.
2. Related Art
Semiconductor chips may be formed on a semiconductor substrate (e.g., a semiconductor wafer) using various unit processes such as: a deposition process, an etching process, a diffusion process, an implantation process, and the like. The semiconductor chips may be evaluated by an electrical test and may be encapsulated or packaged using an assembly process. The assembly process may include mounting each semiconductor chip on a package substrate having external terminals and molding the semiconductor chip to protect it from an external environment. The external terminals may be electrically connected to the semiconductor chip using a wire bonding technique or a bump bonding technique (also, referred to as a flip chip bonding technique).
According to the wire bonding technique, a semiconductor chip may be mounted on a lead frame having a plurality of leads and pads of the semiconductor chip may be electrically connected to the leads through wires such as golden wires. Each of the leads may include an inner lead and an outer lead. The wires may be bonded to the inner leads. According to the bump bonding technique, protruding bumps may be formed on respective pads of the semiconductor chip or respective pads of a package substrate, and the pads of the semiconductor chip may be electrically connected to the pads of the package substrate using the bumps. If the bump bonding technique is used in the assembly process, the semiconductor chip may directly come in contact with the package substrate without use of the bonding wires. Thus, the semiconductor packages that are fabricated using the bump bonding technique can be scaled down in size as compared with the semiconductor packages that are fabricated using the wire bonding technique. Further, the bump bonding technique may lead to minimization of the lengths of interconnection lines between the semiconductor chip and the package substrate. Thus, the impedance of the interconnection lines may be reduced to improve the operation speed of a semiconductor package including the semiconductor chip. Accordingly, there is an increasing demand for the bump bonding technique in assembly processes.
The bumps used in the bump bonding technique may be conductive protrusions for electrically connecting a semiconductor chip to a package substrate with a tape automated bonding (TAB) manner or a flip chip manner or for electrically connecting a ball grid array (BGA) package and/or a chip size package (CSPs) to a circuit board. The bumps may include a gold material. However, in general, the bumps may be formed of a solder material containing lead and tin. Alternatively, the bumps may be formed of an alloy containing tin, silver, and copper. The bumps may have two major roles. One is to increase heights of pads of a semiconductor chip for facilitation of a flip chip package process, and the other is to facilitate the physical contacts between the pads of the semiconductor chip and external terminals of a package substrate.
As the semiconductor packages are continuously scaled down, distances between the bumps have been reduced to increase the probability of electrical shortage between the bumps. This is because a solder material is evenly formed on sidewalls of the bumps when the bumps of the semiconductor chip are bonded to the bumps of the package substrate using the solder material. In addition, when the semiconductor packages are scaled down, adhesion between the bumps of the semiconductor chip and the bumps of the package substrate may affect the reliability of the semiconductor package more.